Fringe RLGC model for interconnect parasitic extraction

ABSTRACT

An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.

FIELD OF THE INVENTION

The present invention generally relates to models for interconnectparasitic extraction and in particular, to a fringe RLGC model forinterconnect parasitic extraction.

BACKGROUND OF THE INVENTION

Interconnect parasitic extraction is useful for analyzing signalpropagation characteristics such as impedance mismatch and timingdelays, as well as ground bounce in power distribution systems. Theextraction of highly accurate interconnect parasitics, however, isdifficult for many complex interconnect structures such as found inintegrated circuits, electronic packages, and printed circuit boards,because of excessive processor and memory requirements.

For example, although three-dimensional (“3-D”) full-wave field solversare known to provide high accuracy in calculating interconnectparasistics, less accurate two-dimensional (“2-D”) field solvers aregenerally employed in the design process to reduce processor and memoryrequirements to practical levels.

To further reduce parasitic extraction time during the designverification phase, a library of pre-computed RLGC (resistance “R”,inductance “L”, conductance “G”, capacitance “C”) functions for a numberof 2-D canonical interconnect structures may be provided. When a 2-Dcross-section of an interconnect matches that of a canonical structurein the library, the pre-computed information stored in the library canbe used to quickly calculate RLGC coefficients for the interconnect.

Interconnect parasitics can be classified as being either area, lateralor fringe parasistics. Area parasistics involve interactions between topand bottom surfaces of two conductive elements disposed vertically withrespect to each other. Lateral parasitics involve interactions betweenopposing side surfaces of two conductive elements disposed horizontallywith respect to each other. Fringe parasistics involve interactionsbetween side surfaces of one conductive element and a top (or bottom)surface of another conductive element disposed below (or above) it.

Various models for interconnect parasitic extraction have been used forgenerating an equivalent circuit or transmission line for simulating aninterconnect. One RC model uses area resistance (“Ra”) and areacapacitance (“Ca”) coefficients for generating an equivalent RC circuit.Another RC model uses fringe capacitance (“Cf”) as well as the arearesistance (“Ra”) and area capacitance (“Ca”) coefficients. An RLCmodel, on the other hand, uses an area inductance (“La”) as well as thearea resistance (“Ra”), area capacitance (“Ca”), and fringe capacitance(“Cf”) coefficients for generating an equivalent RLC circuit forsimulating the interconnect.

None of these approaches, however, succeeds in extracting interconnectparasitic coefficients that accurately simulate interconnect frequencyresponse over a wide range of operation like a 3-D full wave fieldsolver does.

OBJECTS AND SUMMARY OF THE INVENTION

An accurate model for interconnect parasitic extraction is highlydesirable so that its corresponding equivalent circuit or transmissionline accurately simulates an interconnect. Accurate simulation of designinterconnect structures is especially important where signal timing iscritical for correct operation. Accurate simulation is also importantwhere costly and time consuming redesign can be avoided. Avoidingredesign in this case is especially valuable where re-tooling costs arehigh, redesign and/or manufacturing time is lengthy, and product lifecycles are short so that time to market is crucial.

Accordingly, one object of the present invention is to provide a modelfor interconnect parasitic extraction that provide parasiticcoefficients that accurately simulate interconnect frequency responseover a wide range of operation comparable to results achieved using a3-D full-wave field solver approach.

Another object is to provide a model for interconnect parasiticextraction that provides parasitic coefficients that accurately simulateinterconnect frequency response over a wide range of operation that usesprocessor and memory resources comparable to 2-D field solvers models.

Another object is to provide a Resistance, Inductance, Conductance,Capacitance (“RLGC”) library utilizing such a model for generating RLGCcoefficients that define an equivalent RLGC circuit or a set ofS-parameters that accurately simulates an interconnect.

Still another object is to provide a method for generating RLGCcoefficients that define an equivalent RLGC circuit or a set ofS-parameters that accurately simulates an interconnect and is suitablefor irregularly shaped interconnect structures.

These and other objects are accomplished by the various aspects of thepresent invention, wherein briefly stated, one aspect is a method forgenerating an RLGC library, comprising: generating a total inductancefunction for a canonical interconnect structure; generating a fringeinductance function using the total inductance function; and storing thefringe inductance function in an RLGC library.

Another aspect is a method for generating an RLGC library, comprising:generating a total resistance function for a canonical interconnectstructure; generating a fringe resistance function using the totalresistance function; and storing the fringe resistance function in anRLGC library.

Still another aspect is a method for generating an RLGC library,comprising: generating a total conductance function for a canonicalinterconnect structure; generating a fringe conductance function usingthe total conductance function; and storing the fringe conductancefunction in an RLGC library.

Yet another aspect is a method for generating resistance, inductance,conductance, capacitance (“RLGC”) coefficients of an equivalent circuitfor simulating an interconnect structure, comprising: defining aplurality of meshes on a surface of an interconnect structure;calculating at least one area RLGC coefficient for each of the pluralityof meshes; and calculating at least one fringe RLGC coefficient for eachmesh of the plurality of meshes that has an outer edge that does notabut an edge of another mesh of the plurality of meshes.

Additional objects, features and advantages of the various aspects ofthe present invention will become apparent from the followingdescription of its preferred embodiment, which description should betaken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a computer system implementingaspects of the present invention.

FIG. 2 illustrates a flow diagram of a method for generating equivalentRLGC circuits and S-Parameters for simulating selected interconnects,utilizing aspects of the present invention.

FIG. 3 illustrates a flow diagram of a method for building an RLGClibrary, utilizing aspects of the present invention.

FIG. 4 illustrates a cross-sectional view of a first 2-D canonicalinterconnect structure including a homogeneous dielectric layerseparating conductive and power/ground elements.

FIG. 5 illustrates a cross-sectional view of a second 2-D canonicalinterconnect structure including a homogeneous dielectric layerseparating a conductive element from power/ground elements respectivelydisposed above and below the conductive element.

FIG. 6 illustrates a cross-sectional view of a third 2-D canonicalinterconnect structure including inhomogeneous dielectric layer(s)separating conductive and power/ground elements.

FIG. 7 illustrates a cross-sectional view of a fourth 2-D canonicalinterconnect structure including inhomogeneous dielectric layer(s)separating a conductive element from power/ground elements respectivelydisposed above and below the conductive element.

FIG. 8 illustrates a method for generating area and fringe RLGCcoefficients for an interconnect structure, utilizing aspects of thepresent invention.

FIG. 9 illustrates a method for determining an effective interconnectstructure for calculating fringe RLGC coefficients of an edge mesh,utilizing aspects of the present invention.

FIG. 10 illustrates a top plan view of a two-layer interconnectstructure.

FIG. 11 illustrates a front cross-sectional view of the two-layerinterconnect structure of FIG. 10.

FIG. 12 illustrates a top plan view of a layer of an interconnectstructure with representative meshes depicted thereon.

FIG. 13 illustrates a top plan view of the layer of the interconnectstructure depicted in FIG. 12 with a couple of representative edgemeshes and their associated widths depicted thereon.

FIG. 14 illustrates a top plan view of a square plate interconnectstructure.

FIG. 15 illustrates comparative frequency responses of a 3-D full-waveextraction model, area RLGC with fringe capacitance model, and area RLGCwith fringe RLGC model for the square plate interconnect structure ofFIG. 14.

FIG. 16 illustrates a top plan view of a thin micro-strip interconnectstructure.

FIG. 17 illustrates comparative frequency responses of a 3-D full-waveextraction model, area RLGC with fringe capacitance model, and area RLGCwith fringe RLGC model for the thin micro-strip interconnect structureof FIG. 16.

FIG. 18 illustrates a top plan view of a low-pass filter interconnectstructure.

FIG. 19 illustrates comparative frequency responses of a 3-D full-waveextraction model, area RLGC with fringe capacitance model, and area RLGCwith fringe RLGC model for the low-pass filter interconnect structure ofFIG. 18.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A fringe RLGC model is described herein whose various aspects meet theobjectives stated above.

FIG. 1 illustrates, as an example, a block diagram of a computer system100 configured to implement the various methods described herein thatare applicable to designing an integrated circuit, printed circuitboard, integrated circuit package, or other device includinginterconnects for transmitting electrical signals. Included in thecomputer system 100 are a central processing unit (CPU) 101 such asthose typically employed with personal computers or engineering workstations, system memory 102 such as solid state memory, mass storage 110such as one or more hard disk drive units, and a number of input andoutput devices for user interaction with the computer system 100.

Input devices (represented by input device 107) include conventionalitems such as a keyboard and a user manipulated pointing device such asa mouse. Output devices include a display 104 such as a cathode ray tube(CRT) or liquid crystal display (LCD) display screen, as well as otherconventional output devices (represented by output device 112) such as aprinter or a plotter. Also preferably included in the computer system100 is a network interface card 111 for communicating with othercomputers coupled through a network such as a local area network (LAN)or the Internet.

The computer system 100 also includes cooperative software programs anddatabases for design verification. In addition to programs to implementthe various methods described herein, the computer system 100 includes(or is configured with) software programs such as a 2-D field solver, a3-D geometric model generator that generates a 3-D model of a designfrom physical and process design data, a 2-D cross-section generator, apattern matcher (for matching interconnect 2-D cross-sections with 2-Dcanonical interconnect structures), a mesh generator, a circuit solver,and a S-parameter generator. Databases include such items as acomputer-aided design (“CAD”) data file storing physical designinformation, a technology file storing manufacturing processinformation, and an RLGC library. Further details on such softwareprograms and databases are described in the following methods.

FIG. 2 illustrates, as an example, a flow diagram of a method forgenerating equivalent RLGC circuits for simulating selectedinterconnects. In 201, a 3-D model of a design is generated by the 3-Dgeometric model generator from CAD data that specifies the layout of thedesign (such as a GDS-II, MCM, or Gerber file), and a technology fileproviding process information used in fabricating the design (such asconductivities, dielectric constants, permeability values, and losstangents). In 202, the selected interconnect structures in the 3-D modelof the design are identified for processing. Selection in this case maybe by interactive user input or from information stored in a previouslygenerated file.

In 203, each of the interconnect structures is conventionally meshedsuch as described, for example, in Pascal Jean Frey and Paul-LouisGeorge, Mesh Generation: Application to Finite Elements, Hermes SciencePublishing, Oxford, United Kingdom, pp. 116-119; or Albertus J. Kemp,Jacobus A. Pretorius, and Willem Smit, “The Generation of a Mesh forResistance Calculation in Integrated Circuits,” IEEE Transactions onComputer-Aided Design, Vol. 7, No. 10, October 1988, pp. 1029-1037.

For multi-layered interconnect structures, such meshing is performed oneach layer using a layer-by-layer procedure. For example, referring toFIGS. 10 and 11, top plan and front cross-sectional views of a two-layerinterconnect structure 1000 are respectively shown, wherein a bottomconductive element (or layer) 1001 is electrically coupled to a topconductive element (or layer) 1002 by a vertical connection such as avia 1003. In this example, meshing may be performed starting with eitherthe top or bottom layer. The via 1003 in this case is treated as a“point” so that it is effectively ignored for meshing purposes.

Although meshing may be used on a simple interconnect structure such asthe two-layer interconnect structure 1000 in FIGS. 10 and 11, it isparticularly useful when irregularly shaped interconnect structures areto be processed. For example, FIG. 12 illustrates a top plan view of anirregularly shaped layer 1200 of an interconnect structure that includesa hole 1250 which is commonly used, for example in printed circuit boardand packaging designs, for passing connections between layers above andbelow the current layer without connecting to the current layer. Asshown in the figure, the surface of the irregularly shaped layer 1200 ismeshed with a plurality of meshes so as to completely cover its surface.Among the meshes are a number of edge meshes that have at least oneouter edge that does not abut an edge of another mesh in the layer (suchas edge meshes 1201˜1207), and a number of interior meshes having all oftheir edges abutting an edge of another mesh (such as interior meshes1221˜1224).

After meshing each layer of the interconnect structure, in 204, areaRLGC coefficients are generated for all meshes defined on theinterconnect structure, while fringe RLGC coefficients are generated foronly the edge meshes of the interconnect structure. Generation of thefringe RLGC coefficients is preferably performed using an RLGC library.Additional details on the generation of and information included in theRLGC library are described below in reference to FIG. 3, and additionaldetails on the generation of the area and fringe RLGC coefficients arefurther described below in reference to FIGS. 8 and 9.

In 205, a T or Π or transmission line RLGC circuit model is then definedfor each of the meshes using its respective area and fringe RLGCcoefficients. The T or Π or transmission line RLGC circuit models forall of the meshes defined for an interconnect structure are then coupledtogether. One example of such coupling together of T or Π RLGC circuitmodels is described in Joong-Ho Kim and Madhavan Swaminathan, “Modelingof Irregular Shaped Power Distribution Planes Using Transmission MatrixMethod,” IEEE Transactions on Advanced Packaging, Vol. 24, No. 3, August2001, pp. 334-346; and an example of such coupling together oftransmission line RLGC circuit models is described in Henry Hungjen Wu,Jeffrey W. Meyer, Keunmyung Lee, and Alan Barber, “Accurate Power Supplyand Ground Plane Pair Models,” IEEE Transactions on Advanced Packaging,Vol. 22, No. 3, August 1999, pp. 259-266.

In 206, vertical connections (such as vias, bondwires, solder balls, orsolder bumps) in the selected interconnects are identified, andcorresponding equivalent RLGC circuits are associated with the verticalconnections. The equivalent RLGC circuits in this case may have beenpredetermined through empirical testing of previously fabricatedvertical connections or they may be calculated using the 2-D fieldsolver.

In 207, an equivalent RLGC network is formed for each interconnectstructure by coupling the vertical connection RLGC circuits generated in206 to RLGC circuits generated in 205 that correspond to meshes thatabut or include the vertical connections.

In 208, the equivalent RLGC networks for the selected interconnectstructures are then solved or simulated using SPICE or a circuit solverfor their output voltages, currents and/or S-parameters.

FIG. 3 illustrates, as an example, a flow diagram of a method forbuilding an RLGC library such as the one used in the method described inreference to FIG. 2.

In 301, a set of 2-D canonical interconnect structures areconventionally defined so as to be representative of 2-Dcross-sectionals generated for design interconnects. The set of 2-Dcanonical interconnect structures in this case is basically the same asprovided in conventional libraries of this sort. The key differencebetween those libraries and the RLGC library of the present invention isnot their 2-D canonical structures, but the additional fringe RLGCfunctions provided therein.

For illustrative purposes in this example, the RLGC library includesfringe RLGC functions for the 2-D canonical interconnect structuresillustrated in FIGS. 4˜7, wherein FIG. 4 illustrates a cross-sectionalview of a first 2-D canonical interconnect structure 400 including ahomogeneous dielectric layer 402 separating conductive element 401 andpower/ground element 403; FIG. 5 illustrates a cross-sectional view of asecond 2-D canonical interconnect structure 500 including a homogeneousdielectric layer 502 separating a conductive element 501 frompower/ground elements 504 and 503 respectively disposed above and belowthe conductive element 501; FIG. 6 illustrates a cross-sectional view ofa third 2-D canonical interconnect structure 600 including inhomogeneousdielectric layer 602, 605 separating conductive element 601 andpower/ground element 603; and FIG. 7 illustrates a cross-sectional viewof a fourth 2-D canonical interconnect structure 700 includinginhomogeneous dielectric layer 706, 707 separating a conductive element701 from a power/ground element 704 disposed above the conductiveelement 701, and inhomogeneous dielectric layer 702, 705 separating theconductive element 701 from a power/ground element 703 disposed belowthe conductive element 701.

Each of the conductive elements 401, 501, 601, and 701 in FIGS. 4˜7 isrepresentative of an interconnect or net in an integrated circuit, or asignal trace in a printed circuit board or an integrated circuit package(all of which are understood to be included in the term “interconnect”as used herein). Each conductive element serves as a primary path fortransmitting an electrical signal having a frequency “f” in Hertz (orits equivalent “ω” in radians/second), and is conventionallycharacterized by a width “w”, thickness “t” and conductivity “σ”.

Each of the power/ground elements in FIGS. 4˜7, on the other hand, isrepresentative of a power bus, ground plane, or substrate in anintegrated circuit, or a power or ground plane in a printed circuitboard or an integrated circuit device package. Each of the power/groundelements is conventionally characterized by a thickness “t” andconductivity “σ”.

The dielectric layers in FIGS. 4˜7 separate their respective conductiveelements from corresponding power/ground elements. They may be formed ofSiO₂, for example, in an integrated circuit, or other dielectricmaterial conventionally used in integrated circuit, printed circuitboard, or integrated circuit packages. Each dielectric layer ischaracterized by a dielectric constant “ε”, permeability “μ”, and losstangent “tan δ”.

A homogeneous dielectric layer such as 402 in FIGS. 4 and 502 in FIG. 5has the same dielectric constant, permeability, and loss tangentthroughout the layer. An inhomogeneous dielectric layer, on the otherhand, includes two or more regions such as regions 602 and 605 in FIG.6, regions 702 and 705 in FIG. 7, and regions 706 and 707 in FIG. 7,that have different dielectric constants and loss tangents.

After defining the 2-D canonical interconnect structures to be includedin the RLGC library, in 302, a first one of the 2-D canonicalinterconnect structures is prepared for processing by retrieving itsprocess dependent material values (e.g., dielectric constants,permeability values, loss tangents, and conductivities) and structuralvalues (e.g., conductive element to power/ground element distances,dielectric region thicknesses, conductive element widths andthicknesses, and power/ground element thicknesses) from a technologyfile.

In 303, the 2-D field solver is invoked to calculate a total capacitancefunction (C_(t)/l) normalized to a per-unit-length basis, a totalinductance function (L_(t)/l) normalized to a per-unit-length basis, atotal resistance function (R_(t)/l) normalized to a per-unit-lengthbasis, and a total conductance function (G_(t)/l) normalized to aper-unit-length basis for the 2-D canonical interconnect structure overa range of selected width (“w”) values for its conductive element.

In 304, area RLGC coefficients are computed for the 2-D canonicalinterconnect structure. For example, the area capacitance (“Ca”), areaconductance (“Ga”), and area inductance (“La”) coefficients mayrespectively be calculated from the following equations: $\begin{matrix}{{C_{a} - {j \times \frac{G_{a}}{\omega}}} = \frac{ɛ_{eff}^{*}}{d_{eff}}} & (1) \\{{L_{a} = {\mu \times d_{eff}}}{{where},}} & (2) \\{ɛ_{eff}^{*} = {ɛ_{eff} \times \left( {1 - {j \times \tan\quad\delta_{eff}}} \right)}} & (3)\end{matrix}$and determination of the effective dielectric constant (“ε_(eff)”), theeffective loss tangent (“tan δ_(eff)”), and the effective conductiveelement to power/ground element distance (“d_(eff)”) depend on the 2-Dcanonical interconnect structure and its associated process parameters.

For example, for the 2-D canonical interconnect structure 400 of FIG. 4,the effective dielectric constant, effective loss tangent, and effectiveconductive element to power/ground element distance are simply thevalues provided for those parameters in the technology file.

For the 2-D canonical interconnect structure 500 of FIG. 5, theeffective conductive element to power/ground element distance isslightly more complicated, and may be computed from the followingequation: $\begin{matrix}{d_{eff} = {{{d1}//{d2}} = \frac{{\mathbb{d}1} \times {\mathbb{d}2}}{{\mathbb{d}1} + {\mathbb{d}2}}}} & (3)\end{matrix}$The effective dielectric constant and loss tangent for this structureare also simply the values provided for these parameters in thetechnology file, since the dielectric layer 502 is homogeneous.

For the 2-D canonical interconnect structure 600 of FIG. 6, theeffective conductive element to power/ground element distance is simplythe sum of the distances d1 and d2. The area capacitance calculation,however, is slightly more complicated, and may be calculated using thefollowing equation: $\begin{matrix}{\frac{ɛ_{eff}^{*}}{d_{eff}} = {{\frac{ɛ_{1}^{*}}{d1}//\frac{ɛ_{2}^{*}}{d2}} = \frac{\frac{ɛ_{1}^{*}}{d1} \times \frac{ɛ_{2}^{*}}{d2}}{\frac{ɛ_{1}^{*}}{d1} + \frac{ɛ_{2}^{*}}{d2}}}} & (4)\end{matrix}$where “ε₁” and “ε₂” are respectively the complex dielectric constantsfor the dielectric regions 602 and 605, and are similar in form toequation (3). Parameter values for calculating each of these complexdielectric constants can be retrieved from the technology file in thesame manner as those for the complex dielectric constant of equation(3).

For the 2-D canonical interconnect structure 700 of FIG. 7, both theeffective conductive element to power/ground element distance and thearea capacitance calculation are even more complicated, and may becalculated using the following equations: $\begin{matrix}{d_{eff} = {\left( {{d1} + {d2}} \right)//\left( {{d3} + {d4}} \right)}} & (5) \\{\frac{ɛ_{eff}^{*}}{d_{eff}} = {\left( {\frac{ɛ_{1}^{*}}{d1}//\frac{ɛ_{2}^{*}}{d2}} \right) + \left( {\frac{ɛ_{3}^{*}}{d3}//\frac{ɛ_{4}^{*}}{d4}} \right)}} & (6)\end{matrix}$where the symbol “//” indicates the following operation be performed onvariables “a” and “b”: $\begin{matrix}{{a//b} = \frac{a \times b}{a + b}} & (7)\end{matrix}$

Determination of the area resistance (“Ra”) coefficient generally alsodepends on the 2-D canonical interconnect structure and its associatedprocess parameters.

For example, for the 2-D canonical interconnect structure 400 of FIG. 4,the area resistance (“Ra”) coefficient may be calculated using thefollowing equations: $\begin{matrix}{R_{a} = {\sqrt{\frac{\omega \times \mu}{2 \times \sigma_{1}}} + \sqrt{\frac{\omega \times \mu}{2 \times \sigma_{2}}} + R_{dc}}} & (8) \\{R_{dc} = {\frac{1}{\sigma_{1} \times w_{1} \times t_{1}} + \frac{1}{\sigma_{2} \times w_{2} \times t_{2}}}} & (9)\end{matrix}$

Since the area resistance (“Ra”) coefficient is the same for bothhomogeneous and inhomogeneous dielectric layer structures, equations (8)and (9) are also applicable to the 2-D canonical interconnect structure600 of FIG. 6 as well as the structure 400 of FIG. 4. For the 2-Dcanonical interconnect structures 500 of FIGS. 5 and 700 of FIG. 7,however, the area resistance (“Ra”) coefficient equation may beapproximated as follows: $\begin{matrix}{{Ra} = {\left( {\frac{1}{\sigma_{1} \times {t1}} + {\frac{1}{2} \times \sqrt{\frac{\omega \times \mu}{2 \times \sigma_{1}}}}} \right) + \left\{ {\left( {\frac{1}{\sigma_{2} \times {t2}} + \sqrt{\frac{\omega \times \mu}{2 \times \sigma_{2}}}} \right)//\left( {\frac{1}{\sigma_{3} \times {t3}} + \sqrt{\frac{\omega \times \mu}{2 \times \sigma_{3}}}} \right)} \right\}}} & (10)\end{matrix}$where σ₁ and t1 are respectively the conductivity and thickness of theconductive element 501 of FIGS. 5 and 701 of FIG. 7, σ₂ and t2 arerespectively the conductivity and thickness of the lower power/groundelement 503 of FIGS. 5 and 703 of FIG. 7, and σ₃ and t3 are respectivelythe conductivity and thickness of the upper power/ground element 504 ofFIGS. 5 and 704 of FIG. 7.

The area conductance (“Ga”) coefficient, on the other hand, is afunction of the area capacitance (“Ca”) and consequently, can bedetermined for each of the 2-D canonical interconnect structures usingthe above described calculations for the area capacitance (“Ca”)coefficients.

In 305, the fringe RLGC functions are then determined for the 2-Dcanonical interconnect structure using the following equations alongwith the per-unit-length total capacitance (C_(t)/l), per-unit-lengthtotal inductance (L_(t)/l), per-unit-length total resistance (R_(t)/l),and per-unit-length total conductance (G_(t)/l) functions generated in302 and the area RLGC coefficient values calculated in 303 over the samerange of selected width (“w”) values for its conductive element used in302. $\begin{matrix}{\frac{C_{t}}{l} = {{C_{a} \times w} + {2 \times C_{f}}}} & (11) \\{\frac{L_{t}}{l} = \frac{\frac{L_{a}}{w} \times \frac{L_{f}}{2}}{\frac{L_{a}}{w} + \frac{L_{f}}{2}}} & (12) \\{\frac{R_{t}}{l} = \frac{\frac{R_{a}}{w} \times \frac{R_{f}}{2}}{\frac{R_{a}}{w} + \frac{R_{f}}{2}}} & (13) \\{\frac{G_{t}}{l} = {{G_{a} \times w} + {2 \times G_{f}}}} & (14)\end{matrix}$

In 306, the fringe RLGC functions are then stored in the RLGC library soas to be associated with the 2-D canonical interconnect structure.Consequently, when a cross-section of a design interconnect structurematches the 2-D canonical interconnect structure, its associated fringeRLGC functions can be retrieved from the RLGC library and fringe RLGCcoefficients for the design interconnect structure can be readilycalculated through interpolation of the retrieved fringe RLGC functionsby the width (and spacing if appropriate) of a conductive element in thedesign interconnect structure.

In 307, a determination is then made whether there is another 2-Dcanonical interconnect structure to be processed for the RLGC library.If the determination in 307 is NO, then the method ends until additional2-D canonical interconnect structures are defined by going back to 301.On the other hand, if the determination in 307 is YES, then the next oneof the 2-D canonical interconnect structures is prepared for processingby retrieving its process dependent material values and structuralvalues from the technology file, and the method jumps back to 303 toprocess that 2-D canonical interconnect structure.

In the above example, the 2-D canonical interconnect structuresillustrated in FIGS. 4˜7 are each only single conductive elementstructures. If additional 2-D canonical interconnect structures aredefined in 301 having multiple conductive elements on a same metal layer(i.e., disposed horizontally with respect to each other), then the abovemethod to generate an RLGC library as described in reference to FIG. 3would be modified in the following ways. First, the generation of thetotal RLGC functions in 303 would be performed by invoking the 2-D fieldsolver to solve the multiple conductive element structures for selectedspacings (“s”) or distances between adjacent conductive elements in thesame metal layer and for selected widths (“w”) of the conductiveelements. Secondly, in addition to calculating a contribution to thetotal RLGC functions by area parasitics, lateral parasitics should alsobe taken into account when generating the fringe RLGC functions forthose multiple conductive element 2-D canonical interconnect structuresin 305.

FIG. 8 illustrates a method for generating RLGC coefficients for aninterconnect structure, such as performed in 204 of FIG. 2. To begin themethod, in 801, information of a first mesh on a first layer of theinterconnect structure is retrieved.

In 802, area RLGC coefficients for the mesh are calculated “on-the-fly”using area RLGC equations as described in reference to 304 of FIG. 3. Todetermine the appropriate set of area RLGC equations to use, a 2-Dcross-sectional of an interconnect structure is first defined by a planeextending orthogonally through the mesh. Area RLGC equationscorresponding to the thus defined interconnect structure are then usedin the area RLGC calculations with process parameters related to thefabrication of the interconnect structure retrieved from a technologyfile.

In 803, a determination is made whether the current mesh is an edgemesh. An edge mesh in this case is defined as a mesh having at least oneedge that does not abut an edge of another mesh on the same layer. Ifthe determination in 803 is NO (i.e., the current mesh is not an edgemesh), then the method proceeds directly to 805. On the other hand, ifthe determination in 803 is YES (i.e., the current mesh is an edgemesh), then the method first performs 804 before proceeding to 805.

In 804, since the current mesh has been determined to be an edge meshfor the design interconnect structure, fringe RLGC coefficients arecalculated for the mesh using an associated width value and fringe RLGCfunctions retrieved from the RLGC library. Additional details ondetermining the associated width value and appropriate fringe RLGCfunctions to be retrieved from the RLGC library are described inreference to FIG. 9 below. The width of the conductive element for thedesign interconnect structure is then used to interpolate the fringeRLGC coefficients from the fringe RLGC functions retrieved from the RLGClibrary.

In 805, a determination is then made whether the current mesh is a lastmesh to be processed on the current layer of the design interconnectstructure. If the determination in 805 results in a NO (i.e., there isanother mesh to be processed on the current layer), then in 806, themethod retrieves information of the next mesh to be processed, and jumpsback to 802 to process that mesh. On the other hand, if thedetermination in 805 results in a YES (i.e., there are no more meshes tobe processed in the current layer), then in 807, a determination is madewhether the current layer is the last layer of the interconnectstructure to be processed. If the determination in 807 is a YES (i.e.,there are no more layers of the interconnect structure to be processed),then the method ends. On the other hand, if the determination in 807 isNO (i.e., there is another layer of the interconnect structure to beprocessed), then in 808, the method retrieves information for a firstmesh of the next layer to be processed and jumps back to 802 to processthat mesh.

FIG. 9 illustrates a method for determining an effective interconnectstructure for calculating fringe RLGC coefficients of an edge mesh. In901, an associated width for the edge mesh is first determined. In onemethod for determining the associated width value for an edge mesh, aline is first defined such that it is perpendicular to and bisects anouter edge of the edge mesh. As previously described, an “outer edge” isan edge of the edge mesh that does not abut another mesh on the currentlayer being processed.

The associated width value is then determined as the distance along thedefined line from its intersection point with the outer edge to anotherouter edge of another edge mesh. For example, in FIG. 13, an associatedwidth may be determined for an edge mesh 1205 that extends along itsassociated perpendicular line 1315 from a mid-point of an outer edge1305 of the edge mesh 1205 to an outer edge 1301 of another edge mesh1201, and another associated width may be determined for an edge mesh1204 that extends along its associated perpendicular line 1314 from amid-point of an outer edge 1304 of the edge mesh 1204 to an outer edge1306 of another edge mesh 1206 that abuts the hole 1250.

After determining the associated width for the edge mesh, in 902, themethod starts to search in a downward direction from the line used indefining the associated width for a power/ground element. For the 2-Dcanonical interconnect structures 400, 500, 600 and 700 respectively ofFIGS. 4˜7, it is assumed that such a power/ground element will be foundbefore encountering another conductive element. This assumption isgenerally valid in the case of printed circuit board and integratedcircuit design packages, since signal traces in those designs arecommonly sandwiched between power and ground planes to minimizecross-talk between the signal layers. The assumption, however, is notgenerally valid in integrated circuit designs. Therefore, for integratedcircuit designs, either the RLGC library is expanded to include 2-Dcanonical interconnect structures for multiple conductive elements inthe vertical direction, or conductive elements encountered whileperforming 902 (and 907) are ignored. In practice, this second approachhas been used with acceptable results, since the interactions betweenthe conductive elements in this case have been found to be significantlyless than those between a conductive element and a power/ground elementwith respect to fringe RLGC parasistics associated with the conductiveelement.

While performing 902, the method also looks for dielectric regionchanges (i.e., whether the dielectric layer beneath the conductiveelement upon whose surface the edge mesh has been defined is homogeneousor inhomogeneous). Accordingly, a determination of whether it has foundsuch a change is continually performed in 903. If the determination in903 results in a YES (meaning that a dielectric change has been found),then in 904, the method stores the dielectric results (e.g., distancetraversed in the dielectric layer until the dielectric change isdetected, and the dielectric constants for the dielectric regions), andcontinues to search for another dielectric constant change in 903.

Meanwhile, the method continues to search for a power/ground element sothat in 905, a determination is made whether a power/ground element hasbeen found before hitting absolute bottom of the design interconnectstructure. If such a power/ground element is found, then in 906, themethod stores the power/ground results (e.g., distance traversed in thedielectric layer until the power/ground element is detected, and anyprocess parameters read out of the technology file for the power/groundelement), and then proceeds to 907 to perform a similar search in theupward direction. If no power/ground element is found in the 905determination before the search hits absolute bottom of the designinterconnect structure, then the method simply proceeds to 907 toperform the similar search in the upward direction.

In 907˜911, the same procedure as described in reference to 902˜906 isgenerally performed in the upward direction. In particular, if apower/ground element is found while performing 907 in the upwarddirection, then in 911, the method stores the power/ground results, andthen ends. On the other hand, if a power/ground element is not foundwhile performing 907 in the upward direction before the search hits thetop of the design interconnect structure, then the method also ends withan indication of such failure being provided so that the cross-sectionalof the design interconnect structure can be determined.

FIG. 14 illustrates a top plan view of a square plate interconnectstructure 1400. The square plate in this case is a conductive elementhaving a width “W” of 200 mils, a length “L” of 200 mils, and athickness “t1” of 1 mil. It resides on a substrate having a height of 4mils and a dielectric constant “ε” of 4.4, and in a dielectric layeralso having a dielectric constant of “ε” of 4.4. Port locations are inthe centers of a top right quadrant and a bottom left quadrant of thesquare plate, and are shown as X's.

FIG. 15 illustrates comparative comparative frequency responses of a 3-Dfull-wave extraction model 1401, a conventional area RLGC with fringecapacitance model 1402, and an area RLGC with fringe RLGC model 1403 ofthe present invention (also referred to herein simply as the “fringeRLGC model”) for the square plate interconnect structure 1400 of FIG.14.

By inspecting the frequency responses, the interconnect frequencyresponse resulting from the fringe RLGC model 1403 (solid line withsuperimposed squares) is almost identical to that of the 3-D full-waveextraction model 1401 (solid line only). The interconnect frequencyresponse resulting from the area RLGC with fringe capacitance model 1402(solid line with superimposed circles) clearly provides a less accurateresult than that of the fringe RLGC model 1403, especially at highfrequencies. The processor and memory requirements for the fringe RLGCmodel, however, are very close to those of the area RLGC with fringecapacitance, and much less than those of the 3-D full-wave extractionmodel, while computation of the fringe RLGC model is performed 100's oftimes faster than the 3-D full-wave extraction model.

FIG. 16 illustrates a top plan view of a thin trace interconnectstructure 1600. The thin trace in this case is a conductive elementhaving a width “W” of 5 mils, a length “L” of 132 mils, and a thickness“t1” of 1 mil. It resides on a substrate having a thickness of 5 milsand a dielectric constant “ε” of 4.4. Above the thin trace is air havinga dielectric constant of “ε” of 1.0. Port locations are at opposite endsof the thin trace, and are shown as X's.

FIG. 17 illustrates comparative frequency responses of a 3-D full-waveextraction model 1701, a conventional area RLGC with fringe capacitancemodel 1702, and the fringe RLGC model 1703 of the present invention forthe thin trace interconnect structure 1600. By inspecting the frequencyresponses, it is clear that the interconnect frequency responseresulting from the fringe RLGC model 1703 (solid line with superimposedsquares) is much closer to that of the 3-D full-wave extraction model1701 (solid line only) than the interconnect frequency responseresulting from the area RLGC with fringe capacitance model 1702 (solidline with superimposed circles). The processor and memory requirementsfor the fringe RLGC model, however, are very close to that of the areaRLGC with fringe capacitance, and much less than that of the 3-Dfull-wave extraction model, while computation of the fringe RLGC modelis performed 100's of times faster than the 3-D full-wave extractionmodel.

As another example, FIG. 18 illustrates a top plan view of a low-passfilter interconnect structure 1800. The low-pass filter in this case isa conductive element having a width “W1” of 0.33 mm, width “W2” of 0.63mm, width “W3” of 3.42 mm, and width “W4” of 6.73 mm. Conductive elementalso has a length “L1” of 1.64 mm, length “L2” of 1.145 mm, length “L3”of 1.65 mm, and length “L4” of 0.635 mm. The conductive element issymmetrical around both vertical and horizontal axes. The conductiveelement also has a thickness “t1” of 0.06 mm. It resides on a substratehaving a thickness of 0.635 mm and a dielectric constant “ε” of 9.6.Above the low pass filter trace is air having a dielectric constant of“ε” of 1.0. Port locations are at opposite ends of the low-pass filtertrace, and are shown as X's.

A description of such a low-pass filter is described in J. Eric Bracken,Din-Kow Sun, and Zoltan J. Cendes, “S-Domain Methods for SimultaneousTime and Frequency Characterization of Electromagnetic Devices,” IEEETransactions on Microwave Theory and Techniques, Vol. 46, No. 9,September 1998, pp. 1277-1290.

FIG. 19 illustrates comparative frequency responses of a 3-D full-waveextraction model 1901, area RLGC with fringe capacitance model 1902, andarea RLGC with fringe RLGC model 1903 (i.e., the fringe RLGC model) forthe low-pass filter interconnect structure 1800. By inspecting thefrequency responses, it is clear that the interconnect frequencyresponse resulting from the fringe RLGC model 1903 (solid line withsuperimposed squares) is much closer to that of the 3-D full-waveextraction model 1901 (solid line only) than the interconnect frequencyresponse resulting from the area RLGC with fringe capacitance model 1902(solid line with superimposed circles). The processor and memoryrequirements for the fringe RLGC model, however, are again very close tothat of the area RLGC with fringe capacitance model and much less thanthat of the 3-D full-wave extraction model, while computation of thefringe RLGC model is performed 100's of times faster than the 3-Dfull-wave extraction model.

In addition to the above frequency response comparisons, it is alsonoted that the fringe RLGC model provides valid results at DC and lowfrequencies where the 3-D full-wave extraction model breaks down.

Although the various aspects of the present invention have beendescribed with respect to a preferred embodiment, it will be understoodthat the invention is entitled to full protection within the full scopeof the appended claims.

1. A method for generating an RLGC library, comprising: generating atotal inductance function for a canonical interconnect structure;generating a fringe inductance function using the total inductancefunction; and storing the fringe inductance function in an RLGC library.2. The method according to claim 1, wherein the canonical interconnectstructure includes a conductive element having a width so that the totalinductance function is a function of the width, and the generation ofthe total inductance function comprises invoking a 2-D field solver tocalculate total inductance values for the canonical interconnectstructure at selected values of the width.
 3. The method according toclaim 1, wherein the canonical interconnect structure includes a firstconductive element having a first width and a second conductive elementhaving a second width, wherein the first and the second conductiveelements are on a same metal layer of the canonical interconnectstructure and separated by a spacing so that the total inductancefunction is a function of the first width, the second width, and thespacing, and the generation of the total inductance function comprisesinvoking a 2-D field solver to calculate total inductance values for thecanonical interconnect structure at selected values of the first width,the second width, and the spacing.
 4. The method according to claim 1,wherein the generation of the total inductance function comprisesreading process parameters to be associated with the canonicalinterconnect structure from a technology file including suchinformation.
 5. The method according to claim 4, wherein the processparameters characterize a semiconductor process.
 6. The method accordingto claim 4, wherein the process parameters characterize a printedcircuit board manufacturing process.
 7. The method according to claim 4,wherein the process parameters characterize an integrated circuitpackage manufacturing process.
 8. The method according to claim 1,wherein the generation of the fringe inductance function comprisescalculating an area inductance for the canonical interconnect structure,and generating the fringe inductance function using the total inductancefunction and the area inductance for the canonical interconnectstructure.
 9. The method according to claim 8, wherein the canonicalinterconnect structure comprises: a conductive element having a width“w” and providing a transmission path for an electrical signal; apower/ground element providing a return path for inductance generated bythe electrical signal; and a dielectric layer having a permeability “μ”,and separating the conductive and the power/ground elements by adistance “d”.
 10. The method according to claim 9, wherein thegeneration of the fringe inductance function comprises generating thefringe inductance function using the following total inductanceequation:Lt/l=[(La/w)×(Lf/2)]/[(La/w)+(Lf/2)] where Lt/l is the total inductancefunction normalized to a per-unit-length basis, La is the areainductance, and Lf is the fringe inductance function for the canonicalinterconnect structure.
 11. The method according to claim 10, whereinthe fringe induction function is a function of the width “w” of theconductive element.
 12. The method according to claim 11, wherein thegeneration of the fringe induction function comprises calculating fringeinductance values using the total inductance equation for selectedvalues of the width “w”.
 13. The method according to claim 10, whereinthe area inductance is calculated using the following equation:La=μ×d.
 14. The method according to claim 10, wherein the power/groundelement is a ground plane.
 15. The method according to claim 10, whereinthe power/ground element is a power bus.
 16. The method according toclaim 10, wherein the power/ground element is a substrate of anintegrated circuit.
 17. The method according to claim 1, furthercomprising: generating a total resistance function for the canonicalinterconnect structure; generating a fringe resistance function usingthe total resistance function; and storing the fringe resistancefunction in the RLGC library.
 18. The method according to claim 17,wherein the canonical interconnect structure includes a conductiveelement having a width so that the total resistance function is afunction of the width, and the generation of the total resistancefunction comprises invoking the 2-D field solver to calculate totalresistance values for the canonical interconnect structure at selectedvalues of the width.
 19. The method according to claim 17, wherein thecanonical interconnect structure includes a first conductive elementhaving a first width and a second conductive element having a secondwidth, wherein the first and the second conductive elements are on asame metal layer of the canonical interconnect structure and separatedby a spacing so that the total resistance function is a function of thefirst width, the second width, and the spacing, and the generation ofthe total resistance function comprises invoking a 2-D field solver tocalculate total resistance values for the canonical interconnectstructure at selected values of the first width, the second width, andthe spacing.
 20. The method according to claim 17, wherein thegeneration of the total resistance function comprises reading processparameters to be associated with the canonical interconnect structurefrom a technology file including such information.
 21. The methodaccording to claim 17, wherein the generation of the fringe resistancefunction comprises calculating an area resistance for the canonicalinterconnect structure, and generating the fringe resistance functionusing the total resistance function and the area resistance for thecanonical interconnect structure.
 22. The method according to claim 21,wherein the canonical interconnect structure comprises: a conductiveelement having a first width “w1”, a first thickness “t1”, and a firstconductivity “σ1”, and providing a transmission path for an electricalsignal having a frequency “f”; a power/ground element having a secondwidth “w2”, a second thickness “t2”, and a second conductivity “σ2”; anda dielectric layer having a permeability “μ”, and separating theconductive and the power/ground elements by a distance “d”.
 23. Themethod according to claim 22, wherein the generation of the fringeresistance function comprises generating the fringe resistance functionusing the following total resistance equation:Rt/l=[(Ra/w1)×(Rf/2)]/[(Ra/w1)+(Rf/2)] where Rt/l is the totalresistance function normalized to a per-unit-length basis, Ra is thearea resistance, and Rf is the fringe resistance function for thecanonical interconnect structure.
 24. The method according to claim 23,wherein the fringe resistance function is a function of the width “w1”of the conductive element.
 25. The method according to claim 24, whereinthe generation of the fringe resistance function comprises calculatingfringe resistance values using the total resistance equation forselected values of the first width “w1”.
 26. The method according toclaim 23, wherein the area resistance is calculated using the followingequation:Ra=SQRT[(ω×μ)/(2×σ1)]+SQRT[(ω×μ)/(2×σ2)]+Rdc where “ω”=2×Π×f inradians/second, and Rdc is a DC component of the area resistance. 27.The method according to claim 26, wherein the DC component of the arearesistance is calculated using the following equation:Rdc=[1/(σ1×w1×t1)]+[1/(σ2×w2×t2)].
 28. The method according to claim 23,wherein the power/ground element is a ground plane.
 29. The methodaccording to claim 23, wherein the power/ground element is a power bus.30. The method according to claim 23, wherein the power/ground elementis a substrate of an integrated circuit.
 31. The method according toclaim 17, further comprising: generating a total conductance functionfor the canonical interconnect structure; generating a fringeconductance function using the total conductance function; and storingthe fringe conductance function in the RLGC library.
 32. The methodaccording to claim 31, wherein the canonical interconnect structureincludes a conductive element having a width so that the totalconductance function is a function of the width, and the generation ofthe total conductance function comprises invoking a 2-D field solver tocalculate total conductance values for the canonical interconnectstructure at selected values of the width.
 33. The method according toclaim 31, wherein the canonical interconnect structure includes a firstconductive element having a first width and a second conductive elementhaving a second width, wherein the first and the second conductiveelements are on a same metal layer of the canonical interconnectstructure and separated by a spacing so that the total conductancefunction is a function of the first width, the second width, and thespacing, and the generation of the total conductance function comprisesinvoking a 2-D field solver to calculate total conductance values forthe canonical interconnect structure at selected values of the firstwidth, the second width, and the spacing.
 34. The method according toclaim 32, wherein the generation of the total conductance functioncomprises reading process parameters to be associated with the canonicalinterconnect structure from a technology file including suchinformation.
 35. The method according to claim 31, wherein thegeneration of the fringe conductance function comprises calculating anarea conductance for the canonical interconnect structure, andgenerating the fringe conductance function using the total conductancefunction and the area conductance for the canonical interconnectstructure.
 36. The method according to claim 35, wherein the canonicalinterconnect structure comprises: a conductive element having a width“w” and providing a transmission path for an electrical signal having afrequency “f”; a power/ground element; and a dielectric layer separatingthe conductive and the power/ground elements by a distance “d”.
 37. Themethod according to claim 36, wherein the generation of the fringeconductance function comprises generating the fringe conductancefunction using the following total conductance equation:Gt/l=(Ga×w)+2×Gf where Gt/l is the total conductance function normalizedto a per-unit-length basis, Ga is the area conductance, and Gf is afringe conductance for the canonical interconnect structure.
 38. Themethod according to claim 37, wherein the fringe conductance function isa function of the width “w” of the first conductive element.
 39. Themethod according to claim 38, wherein the generation of the fringeconductance function comprises calculating fringe conductance valuesusing the total conductance equation for selected values of the width“w”.
 40. The method according to claim 37, wherein the area conductanceis calculated using the following equation:Ga=ω×Ca×tan δ where “ω”=2×Π×f in radians/second, Ca is an areacapacitance calculated for the canonical interconnect structure, and tanδ is a loss tangent of dielectric between the first and the secondconductive elements.
 41. The method according to claim 37, wherein thepower/ground element is a ground plane.
 42. The method according toclaim 37, wherein the power/ground element is a power bus.
 43. Themethod according to claim 37, wherein the power/ground element is asubstrate of an integrated circuit.
 44. The method according to claim31, further comprising: generating a total capacitance function for thecanonical interconnect structure; generating a fringe capacitancefunction using the total capacitance function; and storing the fringecapacitance function in the RLGC library.
 45. The method according toclaim 44, wherein the generation of the fringe capacitance functioncomprises calculating an area conductance for the canonical interconnectstructure, and generating the fringe capacitance function using thetotal capacitance function and the area capacitance for the canonicalinterconnect structure.
 46. A method for generating an RLGC library,comprising: generating a total resistance function for a canonicalinterconnect structure; generating a fringe resistance function usingthe total resistance function; and storing the fringe resistancefunction in a RLGC library.
 47. The method according to claim 46,wherein the canonical interconnect structure includes a conductiveelement having a width so that the total resistance function is afunction of the width, and the generation of the total resistancefunction comprises invoking a 2-D field solver to calculate totalresistance values for the canonical interconnect structure at selectedvalues of the width.
 48. The method according to claim 46, wherein thecanonical interconnect structure includes a first conductive elementhaving a first width and a second conductive element having a secondwidth, wherein the first and the second conductive elements are on asame metal layer of the canonical interconnect structure and separatedby a spacing so that the total resistance function is a function of thefirst width, the second width, and the spacing, and the generation ofthe total resistance function comprises invoking a 2-D field solver tocalculate total resistance values for the canonical interconnectstructure at selected values of the first width, the second width, andthe spacing.
 49. The method according to claim 46, wherein thegeneration of the total resistance function comprises reading processparameters to be associated with the canonical interconnect structurefrom a technology file including such information.
 50. The methodaccording to claim 49, wherein the process parameters characterize asemiconductor process.
 51. The method according to claim 49, wherein theprocess parameters characterize a printed circuit board manufacturingprocess.
 52. The method according to claim 49, wherein the processparameters characterize an integrated circuit package manufacturingprocess.
 53. The method according to claim 46, wherein the generation ofthe fringe resistance function comprises calculating an area resistancefor the canonical interconnect structure, and generating the fringeresistance function using the total resistance function and the arearesistance for the canonical interconnect structure.
 54. The methodaccording to claim 46, wherein the canonical interconnect structurecomprises: a conductive element having a first width “w1”, a firstthickness “t1”, and a first conductivity “σ1”, and providing atransmission path for an electrical signal having a frequency “f”; apower/ground element having a second width “w2”, a second thickness“t2”, and a second conductivity “σ2”; and a dielectric layer having apermeability “μ”, and separating the conductive and the power/groundelements by a distance “d”.
 55. The method according to claim 54,wherein the generation of the fringe resistance function comprisesgenerating the fringe resistance function using the following totalresistance equation:Rt/l=[(Ra/w)×(Rf/2)]/[(Ra/w)+(Rf/2)] where Rt/l is the total resistancefunction normalized to a per-unit-length basis, Ra is the arearesistance, and Rf is the fringe resistance function for the canonicalinterconnect structure.
 56. The method according to claim 55, whereinthe fringe resistance function is a function of the width “w” of thefirst conductive element.
 57. The method according to claim 56, whereinthe generation of the fringe resistance function comprises calculatingfringe resistance values using the total resistance equation forselected values of the first width “w1”.
 58. The method according toclaim 55, wherein the area resistance is calculated using the followingequation:Ra=SQRT[(ω×μ)/(2×σ1)]+SQRT[(ω×μ)/(2×σ2)]+Rdc where “ω”=2×Π×f inradians/second, and Rdc is a DC component of the area resistance. 59.The method according to claim 58, wherein the DC component of the arearesistance is calculated using the following equation:Rdc=[1/(σ1×w1×t1)]+[1/(σ2×w2×t2)].
 60. The method according to claim 55,wherein the power/ground element is a ground plane.
 61. The methodaccording to claim 55, wherein the power/ground element is a power bus.62. The method according to claim 55, wherein the power/ground elementis a substrate of an integrated circuit.
 63. A method for generating anRLGC library, comprising: generating a total conductance function for acanonical interconnect structure; generating a fringe conductancefunction using the total conductance function; and storing the fringeconductance function in a RLGC library.
 64. The method according toclaim 63, wherein the canonical interconnect structure includes aconductive element having a width so that the total conductance functionis a function of the width, and the generation of the total conductancefunction comprises invoking a 2-D field solver to calculate totalconductance values for the canonical interconnect structure at selectedvalues of the width.
 65. The method according to claim 63, wherein thecanonical interconnect structure includes a first conductive elementhaving a first width and a second conductive element having a secondwidth, wherein the first and the second conductive elements are on asame metal layer of the canonical interconnect structure and separatedby a spacing so that the total conductance function is a function of thefirst width, the second width, and the spacing, and the generation ofthe total conductance function comprises invoking a 2-D field solver tocalculate total conductance values for the canonical interconnectstructure at selected values of the first width, the second width, andthe spacing.
 66. The method according to claim 63, wherein thegeneration of the total conductance function comprises reading processparameters to be associated with the canonical interconnect structurefrom a technology file including such information.
 67. The methodaccording to claim 66, wherein the process parameters characterize asemiconductor process.
 68. The method according to claim 66, wherein theprocess parameters characterize a printed circuit board manufacturingprocess.
 69. The method according to claim 68, wherein the processparameters characterize an integrated circuit package manufacturingprocess.
 70. The method according to claim 63, wherein the generation ofthe fringe conductance function comprises calculating an areaconductance for the canonical interconnect structure, and generating thefringe conductance function using the total conductance function and thearea conductance for the canonical interconnect structure.
 71. Themethod according to claim 70, wherein the canonical interconnectstructure comprises: a conductive element having a width “w” andproviding a transmission path for an electrical signal having afrequency “f”; a power/ground element; and a dielectric layer separatingthe conductive and the power/ground elements by a distance “d”.
 72. Themethod according to claim 71, wherein the generation of the fringeconductance function comprises generating the fringe conductancefunction using the following total conductance equation:Gt/l=(Ga×w)+2×Gf where Gt/l is the total conductance function normalizedto a per-unit-length basis, Ga is the area conductance, and Gf is thefringe conductance function for the canonical interconnect structure.73. The method according to claim 72, wherein the fringe conductancefunction is a function of the width “w” of the first conductive element.74. The method according to claim 73, wherein the generation of thefringe conductance function comprises calculating fringe conductancevalues using the total conductance equation for selected values of thewidth “w”.
 75. The method according to claim 72, wherein the areaconductance is calculated using the following equation:Ga=ω×Ca×tan δ where “ω”=2×Π×f in radians/second, Ca is an areacapacitance calculated for the canonical interconnect structure, and tanδ is a loss tangent between the first and the second conductiveelements.
 76. The method according to claim 71, wherein the power/groundelement is a ground plane.
 77. The method according to claim 71, whereinthe power/ground element is a power bus.
 78. The method according toclaim 71, wherein the power/ground element is a substrate of anintegrated circuit.
 79. A method for generating resistance, inductance,conductance, capacitance (“RLGC”) coefficients of an equivalent circuitfor simulating an interconnect structure, comprising: defining aplurality of meshes on a surface of an interconnect structure;calculating at least one area RLGC coefficient for each of the pluralityof meshes; and calculating at least one fringe RLGC coefficient for eachmesh of the plurality of meshes that has an outer edge that does notabut an edge of another mesh of the plurality of meshes.
 80. The methodaccording to claim 79, wherein the calculation of the at least one areaRLGC coefficient comprises: calculating a corresponding area resistancefor each of the plurality of meshes.
 81. The method according to claim79, wherein the calculation of the at least one area RLGC coefficientcorresponding to the interconnect structure comprises: calculating acorresponding area inductance for each of the plurality of meshes. 82.The method according to claim 79, wherein the calculation of the atleast one area RLGC coefficient corresponding to the interconnectstructure comprises: calculating a corresponding area conductance foreach of the plurality of meshes.
 83. The method according to claim 79,wherein the calculation of the at least one area RLGC coefficientcorresponding to the interconnect structure comprises: calculating acorresponding area capacitance for each of the plurality of meshes. 84.The method according to claim 79, wherein each mesh that has an outeredge that does not abut an edge of another mesh of the plurality ofmeshes is referred to as an edge mesh, and the calculation of the atleast one fringe RLGC coefficient for each edge mesh, comprises:defining a line that is perpendicular to the outer edge of the edgemesh, and bisects the outer edge at a bisection point; determining awidth associated with the edge mesh as a distance extending along thedefined line from the bisection point to an outer edge of another edgemesh; and calculating the at least one fringe RLGC coefficient using thedetermined associated width and information stored in an RLGC libraryfor a 2-D canonical interconnect structure resembling a 2-Dcross-sectional slice of the interconnect structure taken along thedefined line.
 85. The method according to claim 84, wherein the at leastone fringe RLGC coefficient is a fringe inductance, and the informationstored in the RLGC library is a fringe inductance function that isdependent on a width of the canonical interconnect structure.
 86. Themethod according to claim 85, wherein the canonical interconnectstructure comprises: a conductive element having a width “w” andproviding a transmission path for an electrical signal; a power/groundelement providing a return path for inductance generated by theelectrical signal; and a dielectric layer having a permeability “μ”, andseparating the conductive and the power/ground elements by a distance“d”.
 87. The method according to claim 86, wherein the fringe inductancefunction is determinable from the following total inductance equation:Lt/l=[(La/w)×(Lf/2)]/[(La/w)+(Lf/2)] where Lt/l is the a totalinductance function normalized to a per-unit-length basis, La is an areainductance, and Lf is the fringe inductance function for the canonicalinterconnect structure.
 88. The method according to claim 87, whereinthe area inductance “La” is calculated using the following equation:La=p×d.
 89. The method according to claim 84, wherein the at least onefringe RLGC coefficient is a fringe resistance, and the informationstored in the RLGC library is a fringe resistance function that isdependent on a width of the canonical interconnect structure.
 90. Themethod according to claim 89, wherein the canonical interconnectstructure comprises: a conductive element having a first width “w1”, afirst thickness “t1”, and a first conductivity “σ1”, and providing atransmission path for an electrical signal having a frequency “f”; apower/ground element having a second width “w2”, a second thickness“t2”, and a second conductivity “σ2”; and a dielectric layer having apermeability “μ”, and separating the conductive and the power/groundelements by a distance “d”.
 91. The method according to claim 90,wherein the fringe resistance function is determinable from thefollowing total resistance equation:Rt/l=[(Ra/w1)×(Rf/2)]/[(Ra/w1)+(Rf/2)] where Rt/l is a total resistancenormalized to a per-unit-length basis, Ra is the area resistance, and Rfis the fringe resistance function for the canonical interconnectstructure.
 92. The method according to claim 91, wherein the arearesistance is calculated using the following equation:Ra=SQRT[(ω×μ)/(2×σ1)]+SQRT[(ω×μ)/(2×σ2)]+Rdc where “ω”=2×Π×f inradians/second, and Rdc is a DC component of the area resistance. 93.The method according to claim 92, wherein the DC component of the arearesistance is calculated using the following equation:Rdc=[1/(σ1×w1×t1)]+[1/(σ2×w2×t2)].
 94. The method according to claim 84,wherein the at least one fringe RLGC coefficient is a fringeconductance, and the information stored in the RLGC library is a fringeconductance function that is dependent on a width of the canonicalinterconnect structure.
 95. The method according to claim 94, whereinthe canonical interconnect structure comprises: a conductive elementhaving a width “w” and providing a transmission path for an electricalsignal having a frequency “f”; a power/ground element; and a dielectriclayer separating the conductive and the power/ground elements by adistance “d”.
 96. The method according to claim 95, wherein the fringeconductance function is determinable from the following totalconductance equation:Gt/l=(Ga×w)+2×Gf where Gt/l is a total conductance function normalizedto a per-unit-length basis, Ga is an area conductance, and Gf is thefringe conductance function for the canonical interconnect structure.97. The method according to claim 96, wherein the area conductance iscalculated using the following equation:Ga=ω×Ca×tan δ where “ω”=2×Π×f in radians/second, Ca is an areacapacitance calculated for the canonical interconnect structure, and tanδ is a loss tangent of dielectric between the conductive and thepower/ground elements.
 98. The method according to claim 84, wherein theat least one fringe RLGC coefficient is a fringe capacitance, and theinformation stored in the RLGC library is a fringe capacitance functionthat is dependent on a width of the canonical interconnect structure.